SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems.

SuperH 32-bit embedded RISC MCUs and MPUs offer high performance per unit of power (MIPS/W), a more compact size, and high cost performance.

Aug 5, 2019 · The SH-3 is a 32-bit RISC-style (load/store) processor with fixed-length 16-bit instructions. The small instruction size permits higher code density than its contemporaries, with Hitachi claiming a code size reduction of a third to a half …

The architecture in question is Hitachi's SuperH, whose instruction set was a precursor to one used in many ARM Thumb CPUs. But the patents on the most important SuperH designs have all expired—and more will be expiring in the months and years to come—which makes SuperH a candidate for revival.

High performance per unit of power (MIPS/W), more compact size, and high cost performance: SuperH Family 32-bit embedded RISC MCUs & MPUs. CPU cores for a variety of applications and devices, including single-chip controllers, processors, and ASSPs.

The SH-1 is the first CPU core of the SuperH Family products. Featuring 56 basic instructions, the SH-1 contributed to the smaller sizes of digital still cameras, increased functionality of digital notebooks and PDAs, and to the higher capability and lower costs of industrial equipment.

SuperH processor solutions (SH-3/SH-4A) from 200 to 1000DMIPS provide highly integrated systems comprising various connectivity solutions like USB, PCI or 2-channel G-Ether, with multimedia processing capabilities for audio/video encoding and decoding. 32-bit RISC architecture. Superscalar instruction processing. Advanced Cache concepts.