SuperH - Wikipedia
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by …
SuperH RISC Engine Family MCUs | Renesas
SuperH 32-bit embedded RISC MCUs and MPUs offer high performance per unit of power (MIPS/W), a more compact size, and high cost performance.
The SuperH-3, part 1: Introduction - The Old New Thing
Aug 5, 2019 · The SH-3 is a 32-bit RISC-style (load/store) processor with fixed-length 16-bit instructions. The small instruction size permits higher code density than its contemporaries, …
Resurrecting the SuperH architecture - LWN.net
The architecture in question is Hitachi's SuperH, whose instruction set was a precursor to one used in many ARM Thumb CPUs. But the patents on the most important SuperH designs have …
SuperH RISC Engine Family Features | Renesas
High performance per unit of power (MIPS/W), more compact size, and high cost performance: SuperH Family 32-bit embedded RISC MCUs & MPUs. CPU cores for a variety of applications …
SuperH - Renesas Electronics
The SH-1 is the first CPU core of the SuperH Family products. Featuring 56 basic instructions, the SH-1 contributed to the smaller sizes of digital still cameras, increased functionality of digital …
SuperH processor solutions (SH-3/SH-4A) from 200 to 1000DMIPS provide highly integrated systems comprising various connectivity solutions like USB, PCI or 2-channel G-Ether, with …
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