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gicv3 aarch32 icc_hsre - Architectures and Processors forum
When I try to read the ICC_HSRE I get an undefined instruction and the system crashes. The instruction I am using is . mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE. Any idea what is wrong here, and why I get an undefined instruction. In aarch32 EL2, I am pretty sure this is the register that should be used to access the GIC System Register Enable ...
GIC-v3: optional asymetric / legacy support - Arm Community
2016年11月29日 · • ICC_HSRE.SRE. • ICC_MSRE.SRE. • GICD_CTLR.ARE_NS. • GICD_CTLR.ARE_S. A consequence of this is that if a GICv3 implementation supports legacy operation, it will be in legacy mode at reset; so if you're not in legacy mode at reset, your GICv3 implementation does not support legacy operation. Hope that helps, Ash.