
High-k metal gate (HKMG) technology for CMOS devices
High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. This new technology incorporates a high-k dielectric, which reduces leakage and improves the dielectric constant. To help with fermi-level pinning and to allow the gate to be adjusted to low threshold voltages, a metal gate is used instead of a polysilicon gate. By combining the ...
High-k and Metal Gate Transistor Research - Intel
Intel made a significant breakthrough in the 45nm process by using a "high-k" (Hi-k) material called hafnium to replace the transistor's silicon dioxide gate dielectric, and by using new metals to replace the N and PMOS polysilicon gate electrodes. These new materials (along with the right process recipe) reduced the NMOS gate leakage by >25X and PMOS gate leakage by …
High-k/metal gate innovations enabling continued CMOS scaling
High-k dielectrics and metal gate electrodes have entered complementary metal-oxide-semiconductor (CMOS) logic technology, integrated in both gate-first and gate-last schemes. We review gate-first high-k / metal gate (HKMG) innovations enabling continued device scaling to the 22 and 14 nm nodes and beyond. First, we summarize some of the insight that allowed early HKMG challenges such as ...
Technology of High-k/Metal-Gate Stack - ResearchGate
2024年7月1日 · Abstract and Figures The High-k/Metal-Gate Stack (HKMG) technology represents a seminal advancement in semiconductor fabrication, predicated upon the substitution of SiO2 with high-k dielectric ...
SK hynix Leading the Way in the HKMG Revolution
2022年11月8日 · Head of Process Integration Technology Development at SK hynix discusses what HKMG is, and its technological competitiveness.
[Tech Pathfinder] HKMG Process Unlocks Next-Gen Mobile DRAM
2023年5月3日 · This article will summarize the principle of the HKMG process and how this technology was applied to the LPDDR5X and LPDDR5T.
集成电路HKMG工艺简介(Gate First/Gate Last) - 知乎专栏
2024年4月13日 · 一. 为何要使用HKMG工艺?众所周知,集成电路器件尺寸越做越小,使得在面积不变下可以放入更多的晶体管,以提高集成度,提升芯片性能。而器件尺寸的等比例缩小同时体现在水平方向上更短的栅极长度和垂直方向上更浅…
HKMG(High-K 栅氧化物层 +Metal Gate)技术 - 知乎专栏
MOS晶体管需要有较高的栅电容以把电荷吸引至沟道中。这使SiO2栅介质必须非常薄(例如在65 nm工艺中为10.5-12A, 只有4个原子层厚)。当小于这样的厚度时,栅泄漏将增加到不可接受的程度,使传统的按比例尺寸缩小不再…
集成电路制造工艺杂谈(一)HKMG技术概论 - 知乎
众所周知,NMOS管的 栅极和体区需要用氧化层隔离,以达到栅电流为零这一重要目标。现代集成电路工艺的尺寸不断下降,工作电压不断下降,因此 氧化层的厚度也需要下降,常规的氧化层采用厚度大于4nm的多晶硅,这种…
High-k/metal gates in the 2010s - IEEE Xplore
2007 saw the introduction of the first high-k/metal gate (HKMG) devices into the marketplace. This marked the return of metal-gate technology on silicon for the first time since polysilicon gates became ubiquitous in the early 1970s. Intel was the first to use high-k/metal gate in its 45-nm product. Other leading-edge manufacturers have now launched HKMG products in …